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3.3V, PRECISION, 33MHz to 500MHz Precision EdgeTM PROGRAMMABLE LVPECL AND HSTL SY89536L BUS CLOCK SYNTHESIZER
FEATURES
Integrated synthesizer plus fanout buffers, clock dividers, and translator in a single 64-pin package Accepts any reference input between 14MHz to 160MHz (single-ended or differential) 33MHz to 500MHz output frequency range LVPECL and HSTL outputs 3.3V 10% power supply Low jitter: <50ps cycle-to-cycle Low pin-to-pin skew: <50ps TTL/CMOS compatible control logic 3 independently programmable output frequency banks: * 9 differential output pairs @BankB (HSTL) * 2 differential output pairs @BankA (LVPECL) * 2 differential output pairs @BankC (LVPECL) Available in 64-pin EPAD-TQFP Precision EdgeTM
DESCRIPTION
The SY89536L programmable clock synthesizer is part of a 3.3V, high-frequency, precision PLL-based clock synthesizer family optimized for multi-frequency, large clocktree applications. This device integrates the following blocks into a single monolithic IC: * * * * PLL (Phase-Lock-Loop)-based synthesizer Fanout buffer Clock generator (divider) Logic translation (LVPECL, HSTL)
The SY89536L includes a flexible input design that accepts any reference input; single-ended LVTTL/CMOS, SSTL and differential LVPECL, LVDS, HSTL, and CML. This level of integration minimizes the additive jitter and part-to-part skew associated with the discrete alternative, resulting in superior system-level timing as well as reduced board space and power. For applications that must interface to a crystal oscillator, see the SY89531L. Data sheets and support documentation can be found on Micrel's web site at www.micrel.com.
APPLICATIONS
Servers Workstations Parallel processor-based systems Other high-performance computing Communications
PRODUCT SELECTION GUIDE
Input Device SY89531L* SY89532L* SY89533L* SY89534L* SY89535L* SY89536L Crystal X X X X X X Reference BankA LVPECL Output BankB HSTL BankC LVPECL
LVPECL LVPECL LVPECL LVPECL LVDS LVPECL
LVPECL LVPECL LVPECL LVPECL LVPECL LVDS HSTL LVPECL LVPECL
*Refer to individual data sheet for details.
Precision Edge is a trademark of Micrel, Inc.
Rev.: A Amendment: /0
1
Issue Date: June 2003
Micrel
SY89536L
PACKAGE/ORDERING INFORMATION
Ordering Information
NC* GND VCCA VCC_LOGIC VCC_LOGIC OUT_SYNC FSEL_A0 FSEL_A1 FSEL_A2 VCCOA QA0 /QA0 QA1 /QA1 VCCOB QB0
Part Number SY89536LHC
Package Type H64-1
Operating Range Commercial
Package Marking SY89536LHC
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC* NC* NC* GND PSEL1 PSEL0 LOOP_REF LOOP_FILTER GND REFCLK /REFCLK VBB_REF M(3) M(2) M(1) M(0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 /QC1 QC1 /QC0 QC0 VCCOC FSEL_C2 FSEL_C1 FSEL_C0 GND FSEL_B2 FSEL_B1 FSEL_B0 GND VCCOB VCCOB /QB8 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 /QB0 QB1 /QB1 QB2 /QB2 QB3 /QB3 QB4 /QB4 QB5 /QB5 QB6 /QB6 QB7 /QB7 QB8
64-Pin EPAD-TQFP (H64-1)
*NC: Do not connect, leave floating.
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PIN DESCRIPTION
Power
Pin Number 60, 61 62 55 30, 31, 50 21 4, 9, 25, 63, 29 (exposed pad) Pin Name VCC_Logic VCCA VCCOA VCCOB VCCOC GND Pin Function Power for Core Logic: Connect to 3.3V supply. 3.3V power pins are not internally connected on the die, and must be connected together on the PCB. Power for PLL: Connect to "quiet" 3.3V supply. 3.3V power pins are not internally connected on the die, and must be connected together on the PCB. Power for Output Drivers: Connect VCCOA and VCCOC pins to 3.3V supply and VCCOB pins to 1.8V supply. Ground: All GND pins must be tied together on the PCB. Exposed pad must be soldered to a ground plane.
Configuration
Pin Number 4 Pin Name VCO_SEL Pin Function LVTTL/CMOS Compatible Input: Selects between internal or external VCO. When tied LOW (GND) internal VCO is selected. For external VCO, leave floating (default condition is logic HIGH). Internal 25k pull-up. LVTTL/CMOS Compatible Input: Controls input frequency pre divider. Internal 25k pull-up. Default is logic HIGH. See "Pre-Divide Frequency Select" table. Analog Input/Output: Provides the reference voltage for PLL loop filter. Analog Input/Output: Provides the loop filter for PLL. See "External Loop Filter
5, 6 7 8 13,14,15,16 22, 23, 24 26, 27, 28 56, 57, 58 59
PSEL(1:0) LOOP REF LOOP FILTER M (3:0) FSEL_C (2:0) FSEL_B (2:0) FSEL_A (2:0) OUT_SYNC
Considerations" for loop filter values.
LVTTL/CMOS Compatible Input: Used to change the PLL feedback divider. Internal 25k pull-up. M0 = LSB. Default is logic HIGH. See "Feedback Divide Select" table. LVTTL/CMOS Compatible Input: Bank C post-divide select. Internal 25k pull-up. Default is logic HIGH. See "Post-Divide Frequency Select" table. FSEL_C0 = LSB. LVTTL/CMOS Compatible Input: Bank B post-divide select. Internal 25k pull-up. Default is logic HIGH. See "Post-Divide Frequency Select" table. FSEL_B0 = LSB. LVTTL/CMOS Compatible Input: Bank A post-divide select. Internal 25k pull-up. Default is logic HIGH. See Post-Divide Frequency Select" table. FSEL_A0 = LSB. Banks A, B, C Output Synchronous Control: (LVTTL/CMOS compatible). Internal 25k pull-up. After any bank has been programmed, toggle with a HIGH-LOW-HIGH pulse to resynchronize all output banks.
Input/Output
Pin Number 1, 2, 3 10, 11 12 51, 52, 53, 54 Pin Name NC REFCLK, /REFCLK VBB_REF QA1 to QA0 Pin Function No Connect: Leave floating. Reference Input: This flexible input accepts any input TTL/CMOS, LVPECL, LVDS, HSTL, SSTL logic levels. See "Input Interface" section. Reference Output Voltage. Used for single-ended input. Maximum sink/source current = 0.5mA. Bank A 100k LVPECL Output Drivers: Output frequency is controlled by FSEL_A (0:2). Terminate outputs with 50 to VCC -2V. See "Output Termination Recommendations" section. Bank B Output Drivers: Differential HSTL outputs. See "Output Termination Recommendations" section. Output frequency is controlled by FSEL_B (0:2). Bank C 100k LVPECL Output Drivers: Output frequency is controlled by FSEL_C (0:2). Terminate outputs with 50 to VCC-2V. See "Output Termination Recommendations" section. No Connect: Leave floating.
32-49 17, 18, 19, 20 64
QB8 to QB0 QC1 to QC0 NC
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Absolute Maximum Ratings(Note 1)
Supply Voltage (VIN) ................................... -0.5V to +4.0V VCC Pin Potential to Ground Pin (All VCC) .. -0.5V to +4.0V Input Voltage (VIN) ........................................ -0.5V to VCCI DC Output Current (IOUT) LVPECL, HSTL outputs ....................................... -50mA Lead Temperature (soldering, 10 sec.) ..................... 220C Storage Temperature (TS) ....................... -65C to +150C
Operating Ratings(Note 2)
Supply Voltage VCCOA and VCCOC .................................... 3.0V to +3.6V VCCOB ....................................................... 1.6V to +2.0V Ambient Temperature (TA) ............................. 0C to +85C Package Thermal Resistance (Junction-to-Ambient) With Die attach soldered to GND: TQFP (JA) Still-Air .............................................. 23C/W TQFP (JA) 200lfpm ............................................ 18C/W TQFP (JA) 500lfpm ............................................ 15C/W With Die attach NOT soldered to GND, Note 3: TQFP (JA) Still-Air .............................................. 44C/W TQFP (JA) 200lfpm ............................................ 36C/W TQFP (JA) 500lfpm ............................................ 30C/W Package Thermal Resistance (Junction-to-Case) TQFP (JC) ......................................................... 4.0C/W
DC ELECTRICAL CHARACTERISTICS
Power Supply Symbol VCCA VCC_LOGIC VCCOA/C VCCOB ICC
Note 1.
Parameter PLL and Logic Supply Voltage Bank A and C VCC Output Bank B VCC Output LVPECL/HSTL Total Supply Current
Condition Note 4
Min 3.0 3.0 1.6
Typ 3.3 3.3 1.8 230
Max 3.6 3.6 2.0 295
Units V V V mA
Note 5
--
Note 2. Note 3. Note 4. Note 5.
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG conditions for extended periods may affect device reliability. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. It is recommended that the user always solder the exposed die pad to a ground plane for enhanced heat dissipation. VCCA, VCC_LOGIC, VCCOA/C are not internally connected together inside the device. They must be connected together on the PCB. VCCOB is a separate supply. No load. Outputs floating, Banks A, B, and C enabled.
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DC ELECTRICAL CHARACTERISTICS
LVCMOS/LVTTL Input Control Logic (VCCA, VCC_LOGIC, VCCOA/C pins = +3.3V 10%) Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Condition Min 2.0 -- -- -- Typ -- -- -- -- Max -- 0.8 150 -300 Units V V A A
REFCLK (Pins 10, 11) INPUT (All VCC pins except VCCOB = +3.3V 10%, VCCOB = +1.8V 10%) Symbol VID VIH VIL Parameter Differential Input Voltage Input HIGH Voltage Input LOW Voltage Condition Min 100 -- -0.3 Typ -- -- -- Max -- VCC +0.3 -- Units mV V V
100k LVPECL Outputs (All VCC pins except VCCOB = +3.3V 10%, VCCOB = +1.8V 10%) Symbol VOH VOL VID VIH VIL IIH IIL VBB Parameter Output HIGH Voltage Output LOW Voltage Differential Input Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Output Reference Voltage Condition Note 6 Note 6 Note 7 Note 7 Note 7 Min Typ Max Units V V mV mV V V A A V VCC-1.145 VCC-1.020 VCC-0.895 VCC-1.945 VCC-1.820 VCC -1.695 100 200 -- -0.3 -600 -1200 -- -- -- -- -- -- -- -- VCC +0.3 -- -300 -700
VCC-1.325 VCC-1.425 VCC-1.525
HSTL Outputs (Bank B QB0:8) (All VCC pins except VCCOB = +3.3V 10%, VCCOB = +1.8V 10%)(Note 8) Symbol VOUT VOH VOL
Note 6. Note 7.
Parameter Output Voltage Swing Output HIGH Voltage Output LOW Voltage
50 to VCC -2V. Banks A, B, and C enabled. VCC = 3.0V to 3.6V.
Condition
Min -- 1.0 0.2
Typ 800 -- --
Max -- 1.2 0.4
Units mV V V
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AC ELECTRICAL CHARACTERISTICS
VCC_LOGIC = VCCA/C = +3.3V 10%, VCCOB = +1.8V 10% Symbol fIN fOUT tVCO tskew Parameter Reference Input Frequency Output Frequency Range Internal VCO Frequency Range Within Device Skew Within Bank PECL Within Bank HSTL Bank-to-Bank Part-to-Part Skew tLOCK tJITTER Maximum PLL Lock Time Cycle-to-Cycle Jitter Period Jitter tpw (min) Minimum Pulse Width Target PLL Loop Bandwidth Feedback Divider Ratio: 66 Feedback Divider Ratio: 30 tDC tr, tf fOUT Duty Cycle Output Rise/Fall Time (20% to 80%) LVPECL_Out HSTL_Out Note 14 Note 14 Note 14 Note 14 Note 13 Note 13 (Pk-to-Pk) (rms) Note 11 Note 12 Note 9 Note 9 Note 9 Note 10 Condition Min 14 33.33 600 -- -- -- -- -- -- -- 50 -- -- 45 -- 100 -- 5 5 1 -- 500 Typ -- -- -- -- -- 60 -- -- -- 50 -- 1.0 2.0 50 250 -- -- -- -- -- 50 -- Max 160 500 1000 50 75 150 200 10 50 -- -- -- -- 55 400 400 10 -- -- -- -- -- Units MHz MHz MHz ps ps ps ps ms ps ps ps MHz MHz % ps ps ns ns ns VCO clock cycle ns ps
tOUTPUT_RESET tHOLD_FSEL tSETUP_FSEL tOUTPUT_SYNC FSEL-to-Valid Output Transition Time tSETUP_OUT_SYNC
Note 8. Note 9. Note 10. Note 11. Note 12. Note 13. Note 14.
All HSTL outputs loaded with 50 to GND. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same voltage and temperature. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage and temperature. Cycle-to-cycle jitter definition: The variation in period between adjacent cycles over a random sample of adjacent cycle pairs. TJITTER_CC =Tn- Tn+1 where T is the time between rising edges of the output signal. Period Jitter definition: For a specified amount of time (i.e., 1ms), there are N periods of a signal, and Tn is defined as the average period of that signal. Period jitter is defined as the variation in the period of the output signal for corresponding edges relative to Tn. Using recommended loop filter components. See "Timing Diagrams."
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TIMING DIAGRAMS
Conditions: Internal VCO, unless otherwise stated.
VCO
FSEL
001
010
FOUT
OUT_SYNC tOUTPUT_SYNC tOUTPUT_RESET tHOLD_FSEL tSETUP_FSEL TIME
Frequency Programming
VCO (ext.)
FSEL
001
010
FOUT
OUT_SYNC tOUTPUT_SYNC TIME
tOUTPUT_RESET
tSETUP_OUT_SYNC
Frequency Programming (External VCO Clock)
VCO
FSEL
001
010
FOUT
OUT_SYNC
fSEL to VALID OUTPUT TRANSITION TIME
TIME
Output Frequency Updates to Valid Output
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FUNCTIONAL BLOCK DIAGRAM
FSEL_A0 (LSB)
OUT_SYNC
VCC_LOGIC
VCC_LOGIC
FSEL_A1
FSEL_A2
VCCOA
VCCOB
VCCA
/QA1
/QA0
GND
QA0
QA1
NC
NC
NC
NC
1
2
3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49 QB0 48 /QB0
3 VCO_SEL PESL1 PSEL0 LOOPREF LOOPFILTER GND 4 5 6 0 = Use Internal PLL 1 = Bypass Internal PLL (default) 7 8 Mux 1 9 Pre Divider 1, 2, 4, 8 VCC--1.425V Reference or Bandgap Reference
14MHz to 20MHz
47 QB1 46 /QB1 45 QB2 2x 44 /QB2 43 QB3 EN 42 /QB3 41 QB4 40 /QB4
3-Bit Divider A 2, 4, 6, 8, 10, 12,18 5
A
Clock Charge Pump VCO
(600MHz to 1000MHz)
Buf
REFCLK 10 /REFCLK 11
Phase Detector
600MHz to 1000MHz
14MHz to 20MHz
3-Bit Divider B 2, 4, 6, 8, 10, 12, 18
9x B EN 3
39 QB5 38 /QB5 37 QB6 36 /QB6
VBB_REF 12
M-Divide 30, 32, 34, 36, 38, 40, 42, 44, 48, 50, 52, 54, 56, 60, 62, 66 3-Bit Divider C 2, 4, 6, 8, 10, 12, 18 C EN
(MSB) M3 13 M2 14 M1 15 (LSB) M0 16 2x 4
35 QB7 34 /QB7 33 QB8
3 32 /QB8 31 VCCOB 29
GND
30 VCCOB
17
/QC1
18
QC1
19
/QC0
20
QC0
21
VCCOC
22
FSEL_C2
23
FSEL_C1
24
FSEL_C0 (LSB)
25
GND
26
FSEL_B2
27
FSEL_B1
28
FSEL_B0 (LSB)
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SY89536L
FUNCTIONAL DESCRIPTION
At the core of the SY89536L clock synthesizer is a precision PLL driven by a differential or single-ended reference input. For users who wish to supply a crystal input, please use the SY89531L. The PLL output is sent to three banks of outputs. Each bank has its own programmable frequency divider, and the design is optimized to provide very low skew between banks, and very low jitter. PLL Programming and Operation IMPORTANT: If the internal VCO will be used, VCO_SEL must be tied LOW, and ExtVCO pins can be left unconnected. The internal VCO range is 600MHz to 1000MHz, and the feedback ratio is selectable via the MSEL divider control (M3:0 pins). The feedback ratio can be changed without powering the chip down. The PLL output is fed to three banks of outputs: Bank A, Bank B, and Bank C. Banks A and C each have two differential LVPECL output pairs. Bank B has nine differential HSTL output pairs. Each bank has a separate frequency divider circuit that can be reprogrammed on the fly. The FSEL_x0:2 (where x is A, B, or C) pins control the divider value. The FSEL divider can be programmed in ratios from 2 to 18, and the outputs of Banks A, B, and C can be synchronized after programming by pulsing the OUT_SYNC pin HIGH-LOWHIGH. Setting a value of 000 for FSEL is an output disable forcing the Q outputs to be LOW and the /Q outputs to be HIGH. Doing so will decrease power consumption by approximately 5mA per bank. To determine the correct settings for SY89536L follow these steps: 1. Refer to the "Suggested Selections for Specific Customer Applications" section for common applications, as well as the formula used to compute the output frequency. 2. Determine the desired output frequency, such as 66MHz. 3. Choose a reference input frequency between 14MHz and 20MHz. The user can also choose a higher input frequency, and use the PSEL pre-divider to divide it down to the 14MHz to 20MHz range. In this example, we choose 18MHz for the reference input frequency. This results in an input/output ratio of 66/18. 4. Refer to the "Feedback Divide Select" table and the "Post-Divide Frequency Select" table to find values for MSEL and FSEL such that MSEL/FSEL equals the same 66/18 ratio. In this example, values of MSEL=44 and FSEL=12 work. 5. Make sure that REFCLK / PSEL x MSEL is between 600MHz and 1000MHz. The user may need to experiment with different REFCLK input frequencies to satisfy these requirements.
330 0.2F
470pF Loop Filter Loop Reference
Figure 1. External Loop Filter Connection External Loop Filter Considerations The SY89536L features an external PLL loop filter that allows the user to tailor the PLL's behavior to their application and operating environment. We recommend using ceramic capacitors with NPO or X7R dielectric, as they have very low effective series resistance. For applications that require ultra-low cycle-to-cycle jitter, use the components shown in Figure 1. The PLL loop bandwidth is a function of feedback divider ratio, and the external loop filter allows the user to compensate. For instance, the PLL's loop bandwidth can be decreased by using a smaller resistor in the loop filter. This results in less noise from the PLL input, but potentially more noise from the VCO. Refer to "AC Electrical Characteristics" for target PLL loop bandwidth. The designer should take care to keep the loop filter components on the same side of the board and as close as possible to the SY89536L's LOOP_REF and LOOP_FILTER pins. To insure minimal noise pick-up on the loop filter, it is desirable to cut away the ground plane directly underneath the loop filter component pads and traces. However, the benefit may not be significant in all applications and one must be careful to not alter the characteristic impedance of nearby traces. Power Supply Filtering Techniques As with any high-speed integrated circuit, power supply filtering is very important. At a minimum, VCCA, VCC_Logic, and all VCCO pins should be individually connected using a via to the power supply plane, and separate bypass capacitors should be used for each pin. To achieve optimal jitter performance, each power supply pin should use separate instances of the circuit shown in Figure 2.
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SY89536L
Power Supply side Ferrite Bead*
Device side VCC Pins
22F
1F
0.01F
*For VCC_Analog,VCC_TTL, VCC1, use ferrite bead = 200mA, 0.45 DC, Murata P/N BLM21A1025 *For VCCOA,B,C use ferrite bead = 3A, 0.025 DC, Murata, P/N BLM31P005 *Component size: 0805
Figure 2. Power Supply Filtering Output Logic Characteristics See "Output Termination Recommendations" for illustrations. In cases where single-ended output is desired, the designer should terminate the unused complimentary output in the same manner as the normal output that is being used. Unused output pairs can be left floating. LVPECL operation: * Typical voltage swing is 700mVPP to 800mVPP into 50. * Common mode voltage is VCC-1.3V, typical. * 100 termination across the output pair is NOT recommended for LVPECL. See "Output Termination" section, Figures 5 to 7. HSTL operation (Bank B): * Typical voltage swing is 250mVPP to 450mVPP into effective 50.
Thermal Considerations This part has an exposed die pad for enhanced heat dissipation. We strongly recommend soldering the exposed die pad to a ground plane. Where this is not possible, we recommend maintaining at least 500lfpm air flow around the part. For additional information on exposed-pad characteristics and implementation details, see Amkor Technology's web site, www.amkor.com. REFCLK Input Interface The flexible REFCLK inputs are designed to accept any differential or single-ended input signal within 300mV above VCC and 300mV below ground. Do not leave unused REFCLK inputs floating. Tie either the true or complement inputs to ground, but not both. A logic zero is achieved by connecting the complement input to ground with the true input floating. For a TTL input, tie a resistor between the complement input and ground. See "Input Interface" section, Figures 4a through 4h. Input Levels LVDS, CML and HSTL differential signals may be connected directly to the REFCLK inputs. Depending on the actual worst case voltage seen, the minimum input voltage swing varies.
VCC
R2 990 REFCLK R1 825 /REFCLK R1 825 GND
R2 990
Figure 3. Simplified Input Structure
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PRE-DIVIDE FREQUENCY SELECT TABLE (PSEL)
PSEL1 (MSB) 0 0 1 1 PSEL0 0 1 0 1 Reference Input Frequency REFCLK / 8 REFCLK / 4 REFCLK / 2 REFCLK / 1
POST-DIVIDE FREQUENCY SELECT TABLE (FSEL)
FSEL_A2(1) (MSB) 0 0 0 0 1 1 1 1 FSEL_A1(1) 0 0 1 1 0 0 1 1 FSEL_A0(1) (LSB) 0 1 0 1 0 1 0 1 Output Divider Output Disable Function, all outputs: Q = LOW, /Q = HIGH VCO / 2 VCO / 4 VCO / 6 VCO / 8 VCO / 10 VCO / 12 VCO / 18
Note 1. Same dividers apply to FSEL_B (0:2) and FSEL_C (0:2).
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FEEDBACK DIVIDE SELECT TABLE (MSEL)
M3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 M2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCO Frequency(1) REFCLK / PSEL x 34 REFCLK / PSEL x 36 REFCLK / PSEL x 38 REFCLK / PSEL x 40 REFCLK / PSEL x 42 REFCLK / PSEL x 44 REFCLK / PSEL x 48 REFCLK / PSEL x 50 REFCLK / PSEL x 52 REFCLK / PSEL x 54 REFCLK / PSEL x 56 REFCLK / PSEL x 60 REFCLK / PSEL x 62 REFCLK / PSEL x 66 REFCLK / PSEL x 30 REFCLK / PSEL x 32
SUGGESTED SELECTIONS FOR SPECIFIC CUSTOMER APPLICATIONS(Notes 1, 2, 3)
Protocol PCI Fast Ethernet 1/8 FC ESCON Rate (MHz) 33 100 133 200 FSEL (Post Divider) 18 6 6 4 MSEL (Feedback Div.) 36 40 52 50 REFCLK (MHz) 16.67 15 15.36 16 PSEL 1 1 1 1 FOUT 33 100 133 200
FOUT =
Note 1. Note 2. Note 3.
(REFCLK / PSEL x MSEL)
FSEL
600MHz < (REFCLK / PSEL x MSEL) < 1000MHz. 14MHz (REFCLK / PSEL) 20MHz. Where two settings provide the user with the identical desired frequency, the setting with the higher PLL input reference frequency (and lower feedback divider) will usually have lower output jitter. However, the reference input frequency, as well as the VCO frequency, must be kept within their respective ranges.
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INPUT INTERFACE
VCC(DRIVER)
VCC VCC(DRIVER) VCC(DRIVER) VCC VCC(DRIVER)
TTL LVTTL
REFCLK /REFCLK 1% SY89536L REFCLK CML 102 1% /REFCLK SY89536L
Figure 4a. 3.3V "TTL"
Figure 4b. CML DC-Coupled
VCC(DRIVER)
VCC VCC(DRIVER)
REFCLK
2.3V to 2.7V
3.0V to 3.6V
PECL /REFCLK SY89536L 50 1% 50 1%
2.5V LVTTL
REFCLK /REFCLK 1% SY89536L
VCC--2V
Figure 4c. 2.5V "LVTTL"
Figure 4d. 3.3V LVPECL DC-Coupled
VCC(DRIVER)
VCC
VCC
CML 102 1%
REFCLK /REFCLK 3.92k 1% 3.92k 1% SY89536L
REFCLK HSTL /REFCLK 50 50 SY89536L
Figure 4e. HSTL
Figure 4f. CML AC-Coupled (Short Trace Lengths)
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VCC
VCC(DRIVER)
82 1%
82 1%
VCC
REFCLK CML /REFCLK 130 1% 130 1% SY89536L
VCC
REFCLK LVDS 100 1% /REFCLK SY89536L
Figure 4g. CML AC-Coupled (Long Trace Lengths)
Figure 4h. LVDS
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OUTPUT TERMINATION RECOMMENDATIONS
+3.3V
+3.3V
ZO = 50 ZO = 50
R1 130
R1 130
+3.3V
"Source"
R2 82
R2 82
"Destination" Vt = VCC -2V
Figure 5. PECL Parallel Termination Thevenin Equivalent (Note 1)
+3.3V
ZO = 50 ZO = 50 50 50
+3.3V
"Source" 50 Rb
"Destination" C1 (optional) 0.01F
Figure 6. PECL Three-Resistor "Y-Termination" (Notes 1, 2, 3)
+3.3V
ZO = 50 ZO = 50 50 50
+3.3V
Source
Destination
Figure 7. HSTL Differential Termination (Note 1)
Note 1. Note 2. Note 3.
Place termination resistors as close to destination inputs as possible. PECL Y-termination is a power-saving alternative to Thevenin termination. Rb resistor sets the DC bias voltage, equal to Vt. For +3.3V systems Rb = 46 to 50.
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64 LEAD EPAD-TQFP (DIE UP) (H64-1)
+0.05 -0.05 +0.002 -0.002
+0.05 -0.05 +0.012 -0.012
+0.03 -0.03 +0.012 -0.012
+0.15 -0.15 +0.006 -0.006
+0.05 -0.05 +0.002 -0.002
Rev. 02
Package EP- Exposed Pad
Die
CompSide Island
Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane
PCB Thermal Consideration for 64-Pin EPAD-TQFP Package Package Notes: Note 1. Package meets Level 2 moisture sensitivity classification, and is shipped in dry-pack form. Note 2. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 1849 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
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+ 1 (408) 944-0800
FAX
+ 1 (408) 944-0970
WEB
http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2003 Micrel, Incorporated.
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